Making PCB Layouts, Manual routing, Auto-routing, Copper pouring, Updating from Schematic, Manufacturing Output
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We have been updating a PCB design, when opening the layout lots of clearance errors have come up that was not there before, the DRC is finding faults eg gap=0.25 rule=0.3 but when I look at the DRC settings they are set at 0.13. Reloading the DRC settings does not clear the errors
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