Hello
I've got a Pattern that is nothing more than metal (directional coupler) with four ports. Two each of these are actually shorted together (port 1 and 2, then port 3 and 4). The Symbol of course is just four different nodes as is the Pattern. Not unexpectedly this is giving me "Nets merged" errors in the Connectivity Check. It also gives DRC errors.
How can one build the Pattern and its Component Symbol to avoid this?
Thanks
jom
Design Rule Check/Connectivity Issue
Re: Design Rule Check/Connectivity Issue
I'm going to bring this up since I asked this before.
Basically, I've got a PCB design that is a "breakout" board. The inputs in most cases are simply split and routed to more than one output. I need something that schematically separates the nodes but in the layout these are all shorted together. How can this be done to minimize the DRC and schematic errors? If there only a couple of these I could ignore but there will be enough errors to possibly hide a real mistake. Any help would be appreciated.
jom
Basically, I've got a PCB design that is a "breakout" board. The inputs in most cases are simply split and routed to more than one output. I need something that schematically separates the nodes but in the layout these are all shorted together. How can this be done to minimize the DRC and schematic errors? If there only a couple of these I could ignore but there will be enough errors to possibly hide a real mistake. Any help would be appreciated.
jom
Re: Design Rule Check/Connectivity Issue
I'm not sure what you want, but the example below is provided as a starting point for discussion...
Tom
Re: Design Rule Check/Connectivity Issue
Thanks for that. That isn't quite what I need. Here's my version (I hope I upload the pic correctly):
I see that your JPx devices in the schematic separate the nodes....which is what I need. However, the layout won't have the pins from the JPXs (pin 1, pin 2). On the layout the metal would be straight through as shown on my layout. I need different node names on the schematic but they aren't really different nodes in the layout. Does this make any sense? I'm not sure if this will cause a ton of errors...I'm not sure.
jom
I see that your JPx devices in the schematic separate the nodes....which is what I need. However, the layout won't have the pins from the JPXs (pin 1, pin 2). On the layout the metal would be straight through as shown on my layout. I need different node names on the schematic but they aren't really different nodes in the layout. Does this make any sense? I'm not sure if this will cause a ton of errors...I'm not sure.
jom
Re: Design Rule Check/Connectivity Issue
The only thing that comes to mind is to use one net to tie everything together, but label each node separately with unrelated text labels for schematic clarity. Electrically, the nodes would not be on separate nets...
Tom
Re: Design Rule Check/Connectivity Issue
Thanks.
OK, I'll give it a try and see how it affects possible LVS errors.
jom
OK, I'll give it a try and see how it affects possible LVS errors.
jom