Design Rule Check/Connectivity Issue

Making PCB Layouts, Manual routing, Auto-routing, Copper pouring, Updating from Schematic, Manufacturing Output
Post Reply
Message
Author
jom
Posts: 86
Joined: 16 Feb 2012, 09:52

Design Rule Check/Connectivity Issue

#1 Post by jom » 05 Feb 2015, 07:38

Hello

I've got a Pattern that is nothing more than metal (directional coupler) with four ports. Two each of these are actually shorted together (port 1 and 2, then port 3 and 4). The Symbol of course is just four different nodes as is the Pattern. Not unexpectedly this is giving me "Nets merged" errors in the Connectivity Check. It also gives DRC errors.

How can one build the Pattern and its Component Symbol to avoid this?

Thanks

jom

jom
Posts: 86
Joined: 16 Feb 2012, 09:52

Re: Design Rule Check/Connectivity Issue

#2 Post by jom » 07 Mar 2022, 06:15

I'm going to bring this up since I asked this before.

Basically, I've got a PCB design that is a "breakout" board. The inputs in most cases are simply split and routed to more than one output. I need something that schematically separates the nodes but in the layout these are all shorted together. How can this be done to minimize the DRC and schematic errors? If there only a couple of these I could ignore but there will be enough errors to possibly hide a real mistake. Any help would be appreciated.

jom

Tomg
Expert
Posts: 2028
Joined: 20 Jun 2015, 07:39

Re: Design Rule Check/Connectivity Issue

#3 Post by Tomg » 07 Mar 2022, 09:29

I'm not sure what you want, but the example below is provided as a starting point for discussion...
brk1.png
brk1.png (18.91 KiB) Viewed 442 times
Tom

jom
Posts: 86
Joined: 16 Feb 2012, 09:52

Re: Design Rule Check/Connectivity Issue

#4 Post by jom » 07 Mar 2022, 12:54

Thanks for that. That isn't quite what I need. Here's my version (I hope I upload the pic correctly):
Capture.PNG
Capture.PNG (13.15 KiB) Viewed 438 times
I see that your JPx devices in the schematic separate the nodes....which is what I need. However, the layout won't have the pins from the JPXs (pin 1, pin 2). On the layout the metal would be straight through as shown on my layout. I need different node names on the schematic but they aren't really different nodes in the layout. Does this make any sense? I'm not sure if this will cause a ton of errors...I'm not sure.

jom

Tomg
Expert
Posts: 2028
Joined: 20 Jun 2015, 07:39

Re: Design Rule Check/Connectivity Issue

#5 Post by Tomg » 07 Mar 2022, 16:24

The only thing that comes to mind is to use one net to tie everything together, but label each node separately with unrelated text labels for schematic clarity. Electrically, the nodes would not be on separate nets...
brk_sch.png
brk_sch.png (11.91 KiB) Viewed 436 times
Tom

jom
Posts: 86
Joined: 16 Feb 2012, 09:52

Re: Design Rule Check/Connectivity Issue

#6 Post by jom » 08 Mar 2022, 06:20

Thanks.

OK, I'll give it a try and see how it affects possible LVS errors.

jom

Post Reply