Nonsensical DRC errors

Making PCB Layouts, Manual routing, Auto-routing, Copper pouring, Updating from Schematic, Manufacturing Output
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dwvcfii
Posts: 3
Joined: 28 Dec 2014, 16:47

Nonsensical DRC errors

#1 Post by dwvcfii » 01 Jan 2015, 20:40

I'm trying to integrate a Keystone screw terminal into my design:

http://www.keyelco.com/product.cfm/product_id/1534

This part was obviously not in the standard libraries so I built my own pattern and component.

The pattern requires 6 vias, and I'm adding a couple more inside those for an alternative part that is a bit less expensive. So I've drawn a total of 8 vias on the pattern. The goal is to have all of these vias connected electrically and to have identical traces in the pattern on both the top and bottom layers for routing flexibility.

In the pattern editor I connect all vias with traces and then in the component editor map the pins as shown. When laying out the part in PCB I route the appropriate nets to one of the vias and then run DRC. The result is shown...lots of clearance violations with negative numbers (!)

My question is, why do these errors occur and how can I eliminate them?

I did my share of research on this before posting and I see only one reference on this forum to negative DRC errors and it appeared to be fixed a couple years ago. Yet here we are.

I also recall reading another thread in which a user was getting similar negative errors for a thermal pad under a part and the solution was to go back into the pattern editor and right click on the traces and select 'convert to pad' but I see no such option in 2.4.0.2.

Any ideas?
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fluxanode
Posts: 84
Joined: 28 Feb 2014, 21:15

Re: Nonsensical DRC errors

#2 Post by fluxanode » 07 Feb 2015, 15:03

Yeah I have the same type issues, hope someone can answer this...

Alex
Technical Support
Posts: 3261
Joined: 14 Jun 2010, 06:43

Re: Nonsensical DRC errors

#3 Post by Alex » 09 Feb 2015, 10:05

To avoid DRC errors you shouldn't connect pads in Pattern editor. Do it in PCB Layout using traces or copper pour instead shapes.

vbhunt
Posts: 3
Joined: 21 Apr 2015, 18:39

Re: Nonsensical DRC errors

#4 Post by vbhunt » 24 Apr 2015, 11:12

If pads should not be connected in pattern editor but rather in PCB Layout, does this then mean that this pour must be done for each board designed? Does this not defeat the utility of
designing such a pattern? In general, what is the reasoning behind not allowing a pattern to contain vias and copper pours?

dtu2
Expert
Posts: 197
Joined: 20 Jan 2012, 10:50

Re: Nonsensical DRC errors

#5 Post by dtu2 » 25 Apr 2015, 14:31

vbhunt wrote:If pads should not be connected in pattern editor but rather in PCB Layout, does this then mean that this pour must be done for each board designed? Does this not defeat the utility of
designing such a pattern? In general, what is the reasoning behind not allowing a pattern to contain vias and copper pours?
I completely agree. This can be quite tedious, especially if the pads and vias don't lie exactly on the grid. It's a waste of time and error prone to do this mundane task in the PCB editor.

Here is another example of why this is needed. This is a mounting hole pad for an M3 screw with via stitching that is intended to connect to ground. To properly place the vias, one needs to do a bit of geometry and then manually enter each via's coordinates. This may require changing the grid uints, layers, objects and properties not to mention the Design Rules to get the placement and routing of the vias accomplished.

This could still be considered a pattern albeit a complex one. This really should be done only once in the pattern editor to simplify the use of such an object as to eliminate the potential for error when repeating the task and to maximize efficiency.

If this pattern and others like it for different diameter screws and other hardware could be built in the library, it would alleviate the necessity to build it each time.

(BTW, this one example could be done with the 'Pad Ring' option in the Pattern Editor even though it's a mess to place that thing or manually entering a pad ring one pad at a time, but in application, this doesn't actually work. Unless you are extremely fortunate, when you route a trace to the final product, the Design Rules Checker will likely give you a clearance violation between the trace and at least one of the pads in the ring).


Alex, there are couple of examples of why this ability is needed and I would imagine there are many others as well when it comes to interfacing hardware to the pcb.

So, to echo vbhunt's question: "In general, what is the reasoning behind not allowing a pattern to contain vias and copper pours?"

thx

jeff
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Jeff

Alex
Technical Support
Posts: 3261
Joined: 14 Jun 2010, 06:43

Re: Nonsensical DRC errors

#6 Post by Alex » 27 Apr 2015, 09:33

There are no reasons to forbid vias in Pattern editor. But adding vias in Pattern editor is the first step, then we need to change pattern library format, then component library format, then schematic format. Therefore Pattern editor hasn't support vias yet, but it will in future.

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