Schematic Capture verification problem

Drawing Schematics, Hierarchical Design, BOM, Exporting net-lists, etc.
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xfer
Posts: 16
Joined: 20 Jun 2018, 12:34

Schematic Capture verification problem

#1 Post by xfer » 08 May 2020, 16:36

The Beta 3 schematic verification is erroneously generating an error for the MUNxxxx number series of NPN transistors. The emitter pins are defined as "Power" instead of "Passive" and it reports a pin mismatch when the emitter is connected to an output pin (as when using a DTR or CTS pin on a USB bridge IC). It is the only series that I have found with this--all others that I have checked (so far) seem to be OK.

Batiskaff
Posts: 2
Joined: 10 May 2020, 10:27

Re: Schematic Capture verification problem

#2 Post by Batiskaff » 11 May 2020, 04:44

Strange, but emitter labelled as ground in datasheet.
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