Drawing Schematics, Hierarchical Design, BOM, Exporting net-lists, etc.
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Finishing up on this little schematic, which I obtained from an article in ARRL QST magazine, May 2021, page 32, I put in the same circuit into DipTrace and tried to verify the circuit. I get errors on the outputs of U2.1, U2.2, & U2.3: see TDR.png and TDR_err.png. If I disconnect any 2 of the U2s and leave one connected, I get no errors: TDR_err2.png! I sure would like to get rid of the remaining errors when I connect all 3 outputs so I can get on with making a PCB layout!! I sure hope someone knows how to fix this problem as I would really like to get to making a PCB for this project.
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You can open "Verification -> Electrical Rule Setup". There it table that defines when errors and warnings are reported. Please notice output to output connection is considered as error (red cell). You can click on the cell to change the rule to either warning or no error.