1) In the PCB Layout editor create a two-layer PCB and place a through-hole resistor (R1) on the Top layer.
2) Route a trace on the Bottom layer between R1's two pads such that it runs out from underneath R1 before returning. Create a new segment in the middle of the trace and turn it into a standard DipTrace jumper (JP1) for the Top layer.
3) Go to the main menu and choose "Route" > "Layer Setup..." to bring up the Layers dialog window.
4) In the Layers dialog window click on the [Signal/Plane] tab, select/highlight the "Top" layer, set its Layer Type to "Plane", set Plated Holes to "Fixed Ring", set Ring: to "0" and click on "Close". This will eliminate the Top layer pad rings of R1, but not the Top layer trace via rings of JP1.
5) In the main menu choose "Verification" > "Design Rules..." to bring up the Design Rules dialog window.
6) In the Design Rules dialog window click on the [Sizes] tab, disable (uncheck) the [ ]All Layers option, select/highlight only the "Top" layer, set the "Minimum" Ring Size: to "0" and click on "OK". This should prevent Top layer ring size rule violations.
7) When viewing the Top layer, shouldn't JP1's Top layer trace via ring size = 0?
8) After converting JP1's trace vias to static vias, shouldn't JP1's Top layer static via ring size = 0?
9) After hiding JP1's Top layer static via rings and running the DRC, shouldn't there be no errors on the Top layer?
For general questions regarding the software and for all questions that do not fit in any of the threads above.
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