DipTrace 4.0 beta

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DerekG
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Joined: 18 Mar 2014, 08:06
Location: Norfolk Island

Re: DipTrace 4.0 beta

#51 Post by DerekG » 04 Mar 2020, 07:40

mpaalanen wrote:
04 Mar 2020, 02:33
Since in practice you always need to include the drill file ..... when you must manually rename the "through.drl" file ....
Quite right. Most board shops want to see the drill file saved as .txt not .drl ................... so please give us a tick box option to have it saved in the usual format (.txt) instead of .drl

Thanks.
I also sat between Elvis & Bigfoot on the UFO.

Tomg
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Re: DipTrace 4.0 beta

#52 Post by Tomg » 04 Mar 2020, 17:51

Since the Renew Layout from Schematic tool will ignore any component with a one-object pattern due to the possibility of PCB-created pads, it might be a good idea to have the Schematic Editor's Convert to PCB tool also ignore components with one-object patterns. This might help users discover some problems a little earlier in the design processs. See this thread for a typical example - viewtopic.php?f=9&t=13275
Tom

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KevinA
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Joined: 18 Dec 2015, 15:35

Re: DipTrace 4.0 beta

#53 Post by KevinA » 04 Mar 2020, 23:20

Was laying out an 'LGA' pattern, at least that is what Nordic called it, and decided to try 4.0, nope, same issues: No means to name pins the same name ie, Nordic called all Vcc pins 103 as in pin number. I guess Altium Designer, the tool they use, can deal with it. Never dealt with a manufacture that wants you to use their art-work/Layout for your PCB but that is what they want. I asked for the recommenced pattern since all they had was mechanical drawings of the nRF9160 and they insisted I just purchase Altium Designer and use their existing design... Strange group. FYI: They ship their SDK with both big $$ tool chains and you can only burn firmware with a Segger J-Link big $$ tool.

novarm44
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Re: DipTrace 4.0 beta

#54 Post by novarm44 » 05 Mar 2020, 02:42

Tomg wrote:
04 Mar 2020, 17:51
Since the Renew Layout from Schematic tool will ignore any component with a one-object pattern due to the possibility of PCB-created pads, it might be a good idea to have the Schematic Editor's Convert to PCB tool also ignore components with one-object patterns. This might help users discover some problems a little earlier in the design processs. See this thread for a typical example - viewtopic.php?f=9&t=13275
I have changed this for upcoming version (not today's update yet): PCB Layout will remove pads if they were placed in Schematic and currently don't exist there.
3.0 and latest beta keeps any separate pad on PCB, but updates it if exists in Schematic, so ignoring something which exists in Schematic while you back annotate is not a way to go.

novarm44
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Re: DipTrace 4.0 beta

#55 Post by novarm44 » 05 Mar 2020, 03:05

KevinA wrote:
04 Mar 2020, 23:20
Was laying out an 'LGA' pattern, at least that is what Nordic called it, and decided to try 4.0, nope, same issues: No means to name pins the same name ie, Nordic called all Vcc pins 103 as in pin number.
DipTrace beta can deal with it too. Name all Vss pins "103@" or "@103" and you get no error message for similar pin numbers (@ is used just to avoid error message, similar pin numbers without @ works in the same way). Then in PCB/Schematic/Component Editor you will see rat-lines (dotted in PCB and red in others) between pins and you can use that as internal connection (jumper) or connect all pins to the net (options are available by right click on the pin). In Schematic or Component Editor you can connect Vss pin of the schematic symbol to one of 103 pads and get all of them connected.
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novarm44
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Re: DipTrace 4.0 beta

#56 Post by novarm44 » 05 Mar 2020, 09:29

Hi All,

We have updated beta-version today. Please download it here:
https://diptrace.com/download/download-diptrace/

If compare to previous build:
1. All reported and onsite found bugs have been fixed. Export/Import of third-party formats are still in process, so some obvious issues are possible there.
2. Attached pattern windows have resizable lists of components and patterns.
3. Place/Replace/Insert component windows are resizable, pattern preview is also resizable.
4. Additional fields windows in PCB/Schematic and default additional fields in component/pattern editors are resizable.
5. Component marking color in Schematic can be set separately from component graphics color.
6. Pin numbers and pin names in schematic and component editor can be rotated (0,90).
7. Layer display order for mask/paste has been corrected. Also shapes in these layers are displayed as borders (similar to pad mask) if signal layers are also visible.
8. Marking display order has been corrected (now they are always on top of any copper object).
9. Component origin is now displayed only in courtyard layer and hidden for other layer by default (you can display it if you wish). Display if not center option has been removed.
10. Last selected component to grid alignment is saved for all further components in PCB Layout.
11. Automatic search of net list when you connect wire to bus or change connection.
12. Improved IPC-7351 libraries and adding old non-IPC libraries with typical components.

Not all wishes listed in this thread and planned for implementation are integrated yet, but we are working on that!

Regards,
Stanislav

fdemir
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Joined: 15 Jun 2010, 11:47

Re: DipTrace 4.0 beta

#57 Post by fdemir » 05 Mar 2020, 16:07

Hi Stas
1-Is it possible resizable IPC pattern generator in pattern editor.
I use 1366x768 screen resolution. As you can see attached image ı can not click oK or Cancel buttons.

2-Searching componenet takes long time. I mentioned before, standart librararies can not be editted by te user. So if program create index from libraries, i think finding component will take a short time.
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novarm44
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Re: DipTrace 4.0 beta

#58 Post by novarm44 » 05 Mar 2020, 18:22

fdemir wrote:
05 Mar 2020, 16:07
Hi Stas
1-Is it possible resizable IPC pattern generator in pattern editor.
I use 1366x768 screen resolution. As you can see attached image ı can not click oK or Cancel buttons.

2-Searching componenet takes long time. I mentioned before, standart librararies can not be editted by te user. So if program create index from libraries, i think finding component will take a short time.
Hi Fazil,
1. I know about this issue, but pattern generator requires space for some more complex pattern types (not BGA) and it is necessary to make different UI (with frames and scrolls, or more tabs) for low resolution. And it is dynamic window with huge amount of algorithms and elements, including dynamically made UI for each pattern type, so we didn't spend time to optimize it for low resolution yet. Only the solution we already made - you can drag that window by mouse cursor and show ok/cancel buttons.
2. We have made possibility to stop search. Indexing is not easy task as we should search for any part of the name/value/field, not the whole word how indexes usually works. It doesn't depend if it is standard library or designed by customer (any index will be made dynamically during first search). Probably will work on that, but not right now.

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KevinA
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Re: DipTrace 4.0 beta

#59 Post by KevinA » 05 Mar 2020, 20:07

Strange 3D stuff: AMD Radeon R5 200 on test machine, when I loaded the BGA 3D devices in pattern editor Diptrace did a 'walk about' awhile. After I placed the two BGA patterns in PCB editor then tried to preview another 'walk about'. The TQFP part had no issues in pattern editor or PCB editor, I had to create a new PCB for that device since trial version only does 500 pins :cry:
See attached files - I loaded the PCB into 3.1, it barked but loaded, no issues, Nvidia Quadro Video card and that is what is on its way for the test computer, I hate AMD video cards.... a Driver thing.

FYI: The BGA patterns are broken, UltraLibrarian created patterns with 1,2,3,n numbers instead of a grid a1,a2,a3

I just switched Graphic modes, in OpenGL flipping the board around in 3D mode was bad. Windows and 3D ok but shudders

UPDATE:
Hello,

Thank you for contacting the Ultra Librarian team.

We have received your feedback for MAX14690AEWX+ and MAX32650GWQ+, however, I am not sure what issue you are referring to. Pin numbering and pin names appear to match according to the datasheet. Can you please provide more information on the error you are seeing?

Best regards,
Rebekah

and my response:
Both the parts I listed are Ball Grid Array products, they call them WLP which I guess means Wafer Level Product… at any rate they are Grid Array devices meaning letters from the top going down and numbers from the left to the right that maps each physical pin as in A1 top row First pin.
Your patterns has 1,2,3,4,n numbers which are not possible on a BGA type device, ever.

Further, the components that are created by function are wrong, big time.
In computers when you have numbers and sort the numbers become ordered as in 1,2,3,4 or 4,3,2,1 BUT when the numbers are text based they are not numbers anymore, sorting them you have 1,11,12,13~2,20,21
The components are P0.1 style which is another problem when you mix text with number values, in order to sort properly you have to break the objects apart, as ‘text’ + NUMBER + NUMBER + NUMBER – sort the numbers below the decimal point then sort the numbers above the decimal point and finally combine the text to the numbers changing everything back to text, sorted correctly.

And finally, the components are not centered, they appear to be centered on what would be pin 1 not the center of the component as everyone else uses.
Please see attached images

New UPDATE:
Do not use Altium V14 for Ultra Librarian, use Eagle. They still have the pin sorting issue on the component but the pattern works.
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Last edited by KevinA on 06 Mar 2020, 16:09, edited 2 times in total.

Alex
Technical Support
Posts: 3197
Joined: 14 Jun 2010, 06:43

Re: DipTrace 4.0 beta

#60 Post by Alex » 06 Mar 2020, 10:26

KevinA wrote:
05 Mar 2020, 20:07
Strange 3D stuff: AMD Radeon R5 200 on test machine, when I loaded the BGA 3D devices in pattern editor Diptrace did a 'walk about' awhile. After I placed the two BGA patterns in PCB editor then tried to preview another 'walk about'. The TQFP part had no issues in pattern editor or PCB editor, I had to create a new PCB for that device since trial version only does 500 pins :cry:
See attached files - I loaded the PCB into 3.1, it barked but loaded, no issues, Nvidia Quadro Video card and that is what is on its way for the test computer, I hate AMD video cards.... a Driver thing.

FYI: The BGA patterns are broken, UltraLibrarian created patterns with 1,2,3,n numbers instead of a grid a1,a2,a3

I just switched Graphic modes, in OpenGL flipping the board around in 3D mode was bad. Windows and 3D ok but shudders
3D rendering of all BGA balls works slower in Direct3D mode. We will try some optimizations in the next build. Please change graphics mode to OpenGL, it should work faster for rendering BGAs.

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