Who knows via in PCB design?

"How-to" questions from new engineers and designers. Please ask and respond here.
Post Reply
Message
Author
Joyce Taylor
Posts: 6
Joined: 12 Jul 2020, 15:22

Who knows via in PCB design?

#1 Post by Joyce Taylor » 23 Jul 2020, 22:29

Is it recommended to put the vias in the middle of the pad? I am making a 4 layer PCB. I want to connect the SMD(package 1210) components from the 1st layer(signal layer) to 2nd layer (ground). So Can I place the via in the mid of the component pad or should I place it near to the component and connect it through a track?

Thanking in advance.

Alex
Technical Support
Posts: 3897
Joined: 13 Jun 2010, 23:43

Re: Who knows via in PCB design?

#2 Post by Alex » 10 Nov 2020, 21:09

Via in pad are not recommended to use because solder leakage through the hole. The exceptions are small hole vias where risk of leakage is very small , blind vias, tented vias, etc.

mpaalanen
Posts: 47
Joined: 21 Jul 2010, 10:05

Re: Who knows via in PCB design?

#3 Post by mpaalanen » 12 Nov 2020, 09:22

Normally you would want to avoid this for the reason given above.
However, when designing a high frequency circuit the parasitic couplings change the situation. At hundreds of MHz, and definitely in the GHz, the shortest extra traces can introduce significant parasitic capacitances and/or inductances. For example a bypass cap can be rendered completely ineffective if it resonates with the inductive trace stub connecting it to a via.
So, if you are designing a RF board then yes, often via-in-pad is a necessary/beneficial feature. For a low frequency board, not so much. Though remember, that signal frequencies are not the only defining feature, edge rates count equally. A modern logic circuit can snap the signal between states real quick and the transition represents frequencies (remember your Fourier series) possibly in the GHz. So demands to bypassing can still be rigorous.
Anyway, don't put vias in pads as a rule. If the PCB lacks space to route the stubs, use smaller components. 1210 is huge, 0805 is no harder and 0603 is easy after a little practice.
One way to mitigate parasitics for decoupling and bypass is to put the vias on left and right of the pads, not the end.

guy1
Posts: 1
Joined: 10 Oct 2021, 12:00

Re: Who knows via in PCB design?

#4 Post by guy1 » 10 Oct 2021, 13:00

Hello

I agree with the recommendation (not to place a via inside an SMD pad), however, there is confusion with the answers that I'd like to explain and fix.

Firstly, regular multilayer vias have a hole that is plated. The hole in the most simplest case is not shut. Even if you defined a tenting soldermask on top of the via's barrel - when this via will be placed on an SMD pad the tenting will not be produced (since the SMD pad has a soldermask clearance defined on it's pad) - so you end up with an open barrel than can wick solder from the SMD pad.

However, 'via in pad' is actually an accepted term for a legitimate via that is used extensively in more complex PCBs. Via in pad, also called VIPPO - via in pad plated over - is actually covered by an IPC-4761 standard (defined as type 7). This is a special via which is fabricated by adding a plated 'cap' to shut off the hole. The hole is first filled, usually with epoxy, then excess resin is scraped off and lastly, a conductive copper is deposited and plated on both sides of the via to shut the via completely. You can learn more about the via structure in this PCB via guide that I wrote.

Under these circumstances, it is perfectly fine to use via in pad. It is a cost adder, pls note. And normally I agree this should be avoided unless necessary. Another point to note is that you have to specifically require via in pad in your fabrication notes document, and further that the manufacturers specializing in low-cost PCB can't or won't make it.

Post Reply