Problem related to Ratelines and Nets

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sairfan1
Posts: 9
Joined: 22 Mar 2013, 03:31

Problem related to Ratelines and Nets

#1 Post by sairfan1 » 04 Mar 2016, 15:53

Hi, I came across a problem where I'm unable to set hierarchy of nets, it leads me to unwanted messed up ratlines in PCB design application.

Scenario is like this I have an IC U1 and two headers J1 and J2. All patterns has 4 pins each.
In Schematic design, I first connected U1 pins to J1 pins (pins are connected U1-pin1 to J1-pin1 and so on pin4)
Then from J1 pin1 to J2 pin1 in same pattern pin2 to pin2 and so on.

When I import this schematic to PCB designer, U1 ratelines are first connected to J2 and then J1 which is quite opposite of my plan. Please advise how can i fix it.

Thanks.

Tomg
Expert
Posts: 1505
Joined: 20 Jun 2015, 14:39

Re: Problem related to Ratelines and Nets

#2 Post by Tomg » 11 Mar 2016, 16:23

sairfan1 wrote:"...U1 ratelines are first connected to J2 and then J1 which is quite opposite of my plan. Please advise how can i fix it..."
Ratlines only show you which pins are connected, or belong to the same Net. Ratlines are not the actual routing of the traces themselves. You are free to route to the pins as you see fit, as long as the pins being connected by the trace belong to the same Net. As you complete each trace, you will see the Ratline that represents that particular Net connection disappear. Use the Ratlines as a guide to show you how many Nets are left to route.

Helpful Hint: To better organize and simplify the Ratline layout, press softkey f12 at any time. Dense designs have inspired many to refer to the site of all of those crisscrossing Ratlines as the "Ratsnest".
Tom

lawrencejefferson
Posts: 1
Joined: 06 Aug 2016, 07:38
Location: New york, USA

Re: Problem related to Ratelines and Nets

#3 Post by lawrencejefferson » 12 Aug 2016, 14:54

Tomg wrote:
sairfan1 wrote:"...U1 ratelines are first connected to J2 and then J1 which is quite opposite of my plan. Please advise how can i fix it..."
Ratlines only show you which pins are connected, or belong to the same Net. Ratlines are not the actual routing of the traces themselves. You are free to route to the pins as you see fit, as long as the pins being connected by the trace belong to the same Net. As you complete each trace, you will see the Ratline that represents that particular Net connection disappear. Use the Ratlines as a guide to show you how many Nets are left to route.

Helpful Hint: To better organize and simplify the Ratline layout, press softkey f12 at any time. Dense designs have inspired many to refer to the site of all of those crisscrossing Ratlines as the "Ratsnest".
I was looking for this type of problem. Thank you so much for the post and replay ;) Ratlines really worked as a true guide in my plan.
I was able to finish it as I thought.

Tomg
Expert
Posts: 1505
Joined: 20 Jun 2015, 14:39

Re: Problem related to Ratelines and Nets

#4 Post by Tomg » 20 Dec 2016, 08:21

Makayla19 wrote:"...when i press f12 nothing happens... ...it wont show any thing..."
The attached video will demonstrate where to find the settings for viewing ratlines and how optimizing them changes their paths. This is a simple circuit, so pressing F12 near the end of the video will change only a few of the ratlines. Remember, optimizing ratlines by pressing F12 will only re-arrange them into the shortest, most direct paths possible to show all of the net connections. It will not tell you how to route your traces. If the ratlines cannot be optimized further, pressing F12 will not make any changes.

p.s. If there is no related schematic, there will be no nets and no associated ratlines until traces (or manual ratlines) have been placed on the PCB layout to make connections. If a trace is unrouted (not deleted), a ratline representing its net connection will appear.
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Tom

Aurora
Posts: 1
Joined: 26 Aug 2017, 18:23

Re: Problem related to Ratelines and Nets

#5 Post by Aurora » 27 Aug 2017, 19:43

sairfan1 wrote:Hi, I came across a problem where I'm unable to set hierarchy of nets, it leads me to unwanted messed up ratlines in PCB design application.

Scenario is like this I have an IC U1 and two headers J1 and J2. All patterns has 4 pins each.
In Schematic design, I first connected U1 pins to J1 pins (pins are connected U1-pin1 to J1-pin1 and so on pin4)
Then from J1 pin1 to J2 pin1 in same pattern pin2 to pin2 and so on.

When I import this schematic to PCB designer, as i was looking for annabolic steroids wich is the best and found https://legalsteroids.best/ U1 ratelines are first connected to J2 and then J1 which is quite opposite of my plan. Please advise how can i fix it.

Thanks.
Never mind, I found it. I can edit the property of a net called "No_rat" and set it to true. later, I will have to remember to remove this property on the nets I modified.

Aurora

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