My mistake !
Sorry for the bother.
Andre

I have tried the latest version of Diptrace but my problem remains. When I export the PnP file for the Panelized PCB, everything seems in order; cordinates for the 4x4 matrix of PCB's. However, when I export the BOM file for the same Panelized PCB, (4x4 matrix), the resulting Exported file is for on...

Thanks again Tom !
May you enjoy Summer.
Andre

Yes, you are correct. The plates were added to the signal layers; top and bottom. I did assign all of the vias to the appropiate Net, a rather tedious job. However, I was unable to assign the plates to the Net. I could not find a command to do so. Can you explain HOW ? Also, maybe you can suggest a ...

No, they are not "copper poured".
They were created with the "drawing tool" and assigned to the different layers.

I'm sure that I must be doing something wrong, but I can't figure out what. When I attach a "Top" layer based heatsink plate to a "Bottom" layer heatsink plate, by using static Vias; I get a small red circle error for each of the Vias, inspite of attaching to the proper NEts, both "plates". This ren...

Found it in sheet settings

Is there a way to scale up the size of the Schematic Worksheet ?
Andre

Forgive my ignorance but does Diptrace, in particular the Autorouting and Auto Placement functions, take significant advantage of Intel Mullti-Core CPUs ?
In short, will I see a signicicant increase in thee speed of these functions by using a CPU with 3X the number of cores ?
Andre

Also, may I ask if a pattern for "Stamp Holes" or "Mouse Bites" can be found in Ver. 4 ? Are there any plans to allow for the rotation of individual "Copies" in the panelization function.
Thank you.