Search found 56 matches

by agareau
27 Sep 2022, 23:31
Forum: DipTrace PCB Layout
Topic: Exporting a BOM for a Panelized PCB
Replies: 1
Views: 1113

Re: Exporting a BOM for a Panelized PCB

My mistake !
Sorry for the bother.
Andre
by agareau
26 Sep 2022, 07:16
Forum: DipTrace PCB Layout
Topic: Exporting a BOM for a Panelized PCB
Replies: 1
Views: 1113

Exporting a BOM for a Panelized PCB

I have tried the latest version of Diptrace but my problem remains. When I export the PnP file for the Panelized PCB, everything seems in order; cordinates for the 4x4 matrix of PCB's. However, when I export the BOM file for the same Panelized PCB, (4x4 matrix), the resulting Exported file is for on...
by agareau
03 Jul 2022, 02:54
Forum: DipTrace PCB Layout
Topic: Errors generated by Vias joining a Top and Bottom heatsink plate.
Replies: 7
Views: 1409

Re: Errors generated by Vias joining a Top and Bottom heatsink plate.

Yes, you are correct. The plates were added to the signal layers; top and bottom. I did assign all of the vias to the appropiate Net, a rather tedious job. However, I was unable to assign the plates to the Net. I could not find a command to do so. Can you explain HOW ? Also, maybe you can suggest a ...
by agareau
29 Jun 2022, 04:18
Forum: DipTrace PCB Layout
Topic: Errors generated by Vias joining a Top and Bottom heatsink plate.
Replies: 7
Views: 1409

Re: Errors generated by Vias joining a Top and Bottom heatsink plate.

No, they are not "copper poured".
They were created with the "drawing tool" and assigned to the different layers.
by agareau
28 Jun 2022, 07:26
Forum: DipTrace PCB Layout
Topic: Errors generated by Vias joining a Top and Bottom heatsink plate.
Replies: 7
Views: 1409

Errors generated by Vias joining a Top and Bottom heatsink plate.

I'm sure that I must be doing something wrong, but I can't figure out what. When I attach a "Top" layer based heatsink plate to a "Bottom" layer heatsink plate, by using static Vias; I get a small red circle error for each of the Vias, inspite of attaching to the proper NEts, both "plates". This ren...
by agareau
10 Jun 2022, 19:59
Forum: Other questions and issues
Topic: Schematic Worksheet
Replies: 1
Views: 1384

Re: Schematic Worksheet

Found it in sheet settings
by agareau
10 Jun 2022, 19:53
Forum: Other questions and issues
Topic: Schematic Worksheet
Replies: 1
Views: 1384

Schematic Worksheet

Is there a way to scale up the size of the Schematic Worksheet ?
Andre
by agareau
30 Jan 2022, 13:08
Forum: Off-topic
Topic: Usage of Intel Multi-Core CPUs
Replies: 1
Views: 3333

Usage of Intel Multi-Core CPUs

Forgive my ignorance but does Diptrace, in particular the Autorouting and Auto Placement functions, take significant advantage of Intel Mullti-Core CPUs ?
In short, will I see a signicicant increase in thee speed of these functions by using a CPU with 3X the number of cores ?
Andre
by agareau
31 May 2020, 21:30
Forum: PCB Manufacturing Questions
Topic: Panelizing: How to specify V-score or tab-route?
Replies: 15
Views: 41990

Re: Panelizing: How to specify V-score or tab-route?

Also, may I ask if a pattern for "Stamp Holes" or "Mouse Bites" can be found in Ver. 4 ? Are there any plans to allow for the rotation of individual "Copies" in the panelization function.
Thank you.