Superimposed pins

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steve65
Posts: 33
Joined: 14 Jun 2010, 05:59

Superimposed pins

#1 Post by steve65 » 17 Sep 2017, 07:49

The Electrical Rule Setup panel has five "Rules to Check", one of which is "Pin Superimposing". Schematic Help advises that activating this rule means that "DipTrace will consider all superimposed pins as errors."

What are superimposed pins?

Thanks.

Steve

Tomg
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Posts: 2028
Joined: 20 Jun 2015, 07:39

Re: Superimposed pins

#2 Post by Tomg » 17 Sep 2017, 13:24

The DipTrace tutorial definition: "Pin Superimposing – the program searches for pins overlaying each other"

When only the [X]Pin Superimposing option is enabled in the ERC setup, superimposed pins will not be reported as being "superimposed". Instead, they will be ambiguously reported as not being connected. For example...
"Error - No Pin Connection: U1: Input A"
"Error - No Pin Connection: U2: Input A"

This is identical to the error message generated when only the [X]Not Connected Pins option is enabled. Seems to me that the ERC error message for the same two "superimposed pins" should read something like the following...
"Error - Superimposed Pins: U1(Input A), U2(Input A)"
Tom

steve65
Posts: 33
Joined: 14 Jun 2010, 05:59

Re: Superimposed pins

#3 Post by steve65 » 17 Sep 2017, 15:42

So superimposing pins are pins that physically overlay one another in the schematic drawing?

Tomg
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Joined: 20 Jun 2015, 07:39

Re: Superimposed pins

#4 Post by Tomg » 17 Sep 2017, 23:51

Yes. That is my interpretation. To me, error reporting for "Pin Superimposing" is too ambiguous and could be confused with "Not Connected Pins" error reporting. Also, if overlapping pins are connected there will be no "Pin Superimposing" errors reported (even if they are not even connected to each other). Here are some examples...
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Tom

steve65
Posts: 33
Joined: 14 Jun 2010, 05:59

Re: Superimposed pins

#5 Post by steve65 » 18 Sep 2017, 07:20

Thanks Tom. That clarifies the topic as well as some of the curious behavior I was seeing with the ERC Pin Superimposing rule.

Steve

arielberschadsky
Posts: 21
Joined: 07 Jul 2018, 10:22

Re: Superimposed pins

#6 Post by arielberschadsky » 26 Feb 2023, 12:56

I still do not understand...why is there even a "pin superimposing" notification, if all it means is that in the schematic there are wires that are overlapping? In some layouts, it's impossible to draw wires from one IC to another without wires overlapping. Moreover, what does "pin superimposing" have to do with "no connection"? I have a working device in which the Diptrace schematic gave me dozens of "pin superimposing" notices. So I don't see the point of that notice.

Tomg
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Posts: 2028
Joined: 20 Jun 2015, 07:39

Re: Superimposed pins

#7 Post by Tomg » 13 Apr 2023, 15:37

It seems like a useful subset of the ERC tool to me, as long as it is properly implemented. The "pins superimposing" check needs debugging. As for wires, here is an example of superimposed wires...
sw1.png
sw1.png (14.5 KiB) Viewed 2021 times
So Is this the actual circuit?...
sw2.png
sw2.png (16.44 KiB) Viewed 2021 times
...or is it this one?...
sw3.png
sw3.png (17.21 KiB) Viewed 2021 times
Tom

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