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 Post subject: Lack of Sheet Connector
PostPosted: 23 May 2016, 16:35 

Joined: 19 May 2016, 16:36
Posts: 2
I am evaluating DipTrace as an alternative to Altium with whom I have become disenchanted. So far I have been heading towards purchase. I have run into my first stumbling block which I would like to post as an issue as opposed to a feature request. There is apparently no true Sheet Connector.

I note that there have been prior posts on this topic but, unless I am missing something, not in recent months. I realize that you can manually come close to a sheet connector using a Net Port. This seems labor intensive and there is a risk. If you are not diligent in renaming the Net Port before connecting it you can easily short nets. This is problematic if you do not notice it while you still have the option to use Undo. The manual process leads to frustration and wasted time.

Realize that the schematic not only defines the design for layout but documents the circuit for later reference. While sheet connectors are not required for successful layout they are certainly critical in debugging and repair.

I can suggest a few possible enhancements to existing components any one of which would improve if not resolve the issue.

* Be able to define default Markings for a component.

In manually simulating a sheet connector you may wish to have both the Main and Additional markings be "None". Or, if you use one of the parameters you may wish to have the default justify be "Center". I realize that as a work-around you can place and customize a component and then copy and past it as needed.

* Allow the connected Net Name to be displayed as a Pin Name.

This could be done by supplying a Show Net checkbox in Pin Properties but could also be achieved as a default should the Pin Name be defined as blank (or some special character). This would allow the text in the simulated sheet connector to track net name changes without risk of design error.

* Allow a Symbol to be placed without a RefDes.

You could simulate a sheet connector as a symbol/component but then they show up in the list of devices as circuit components. The solution might be to define a special RefDes character (maybe just set it blank) that would exclude the simulated sheet connector (or any other symbol that you want) from the part list. This would let you avoid using Net Port and avoid net alteration issues. I assume too that you would then not be forced to place those components on the PCB for routing.

There might be some other small tweaks that would open up flexibility letting us define a sheet connector. Of course you could just add a Sheet Connector type (or Signal Port) if you prefer.

I understand that the package is a PCB layout package and that sheet connectors are not required for that purpose. The better the documentation the less chance of error. No body wants to have to go immediately to Rev 01 over an uncaught netlist error.

Any chance of something like this coming along in the near future? Sadly, it is clouding my purchase decision. My test circuit has grown large enough that I need to spread it across pages or figure out how to work with C size schematics.

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